// ******************************************************************************
// Copyright     :  Copyright (C) 2019, Hisilicon Technologies Co. Ltd.
// File name     :  stfisch_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2018/9/28
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V5.1
// History       :  xxx 2019/08/26 16:45:09 Create file
// ******************************************************************************

#ifndef STFISCH_REG_OFFSET_H
#define STFISCH_REG_OFFSET_H

/* QU_STFISCH_CSR Base address of Module's Register */
#define CSR_QU_STFISCH_CSR_BASE (0x4000)

/* **************************************************************************** */
/*                      QU_STFISCH_CSR Registers' Definitions                            */
/* **************************************************************************** */

#define CSR_QU_STFISCH_CSR_CNB_INT_VECTOR_REG (CSR_QU_STFISCH_CSR_BASE + 0x0)              /* 中断向量 */
#define CSR_QU_STFISCH_CSR_ISCH_INT_REG (CSR_QU_STFISCH_CSR_BASE + 0x4)                    /* 中断状态 */
#define CSR_QU_STFISCH_CSR_ISCH_INT_EN_REG (CSR_QU_STFISCH_CSR_BASE + 0x8)                 /* 中断使能。 */
#define CSR_QU_STFISCH_CSR_ISCH_TH_RLS_C_ERROR_STATUS_REG (CSR_QU_STFISCH_CSR_BASE + 0x10) /* 线程释放冲突。 */
#define CSR_QU_STFISCH_CSR_ISCH_TIME_OUT_ERROR_STATUS_REG (CSR_QU_STFISCH_CSR_BASE + 0x14) /* 线程占用超时中断 */
#define CSR_QU_STFISCH_CSR_ISCH_FQ_TILE_MAP_REG (CSR_QU_STFISCH_CSR_BASE + 0x18)           /* FQ MAP 寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_BP_CTRL_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C)               /* ISCH反压控制寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_FORCE_RLS_CTRL_REG (CSR_QU_STFISCH_CSR_BASE + 0x20)        /* ISCH强制释放寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_MOD_REG (CSR_QU_STFISCH_CSR_BASE + 0x24)                   /* ISCH模式控制寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_TILE_EN_REG (CSR_QU_STFISCH_CSR_BASE + 0x28)               /* TILE使能开关 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x30)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x34)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x38)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x40)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x44)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x48)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x50)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x54)            /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x58)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x60)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x64)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x68)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x70)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x74)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x78)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x80)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x84)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x88)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x90)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x94)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x98)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_28_REG (CSR_QU_STFISCH_CSR_BASE + 0xA0)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_29_REG (CSR_QU_STFISCH_CSR_BASE + 0xA4)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_30_REG (CSR_QU_STFISCH_CSR_BASE + 0xA8)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_31_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_32_REG (CSR_QU_STFISCH_CSR_BASE + 0xB0)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_33_REG (CSR_QU_STFISCH_CSR_BASE + 0xB4)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_34_REG (CSR_QU_STFISCH_CSR_BASE + 0xB8)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_35_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_36_REG (CSR_QU_STFISCH_CSR_BASE + 0xC0)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_37_REG (CSR_QU_STFISCH_CSR_BASE + 0xC4)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_38_REG (CSR_QU_STFISCH_CSR_BASE + 0xC8)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_39_REG (CSR_QU_STFISCH_CSR_BASE + 0xCC)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_40_REG (CSR_QU_STFISCH_CSR_BASE + 0xD0)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_41_REG (CSR_QU_STFISCH_CSR_BASE + 0xD4)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_42_REG (CSR_QU_STFISCH_CSR_BASE + 0xD8)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_43_REG (CSR_QU_STFISCH_CSR_BASE + 0xDC)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xE0)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xE4)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xE8)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xEC)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xF0)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xF4)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xF8)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xFC)           /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_52_REG (CSR_QU_STFISCH_CSR_BASE + 0x100)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_53_REG (CSR_QU_STFISCH_CSR_BASE + 0x104)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_54_REG (CSR_QU_STFISCH_CSR_BASE + 0x108)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_55_REG (CSR_QU_STFISCH_CSR_BASE + 0x10C)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_56_REG (CSR_QU_STFISCH_CSR_BASE + 0x110)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_57_REG (CSR_QU_STFISCH_CSR_BASE + 0x114)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_58_REG (CSR_QU_STFISCH_CSR_BASE + 0x118)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_59_REG (CSR_QU_STFISCH_CSR_BASE + 0x11C)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_60_REG (CSR_QU_STFISCH_CSR_BASE + 0x120)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_61_REG (CSR_QU_STFISCH_CSR_BASE + 0x124)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_62_REG (CSR_QU_STFISCH_CSR_BASE + 0x128)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE_CFG_63_REG (CSR_QU_STFISCH_CSR_BASE + 0x12C)          /* core属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x130)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x134)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x138)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x13C)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x140)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x144)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x148)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x14C)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x150)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x154)        /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x158)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x15C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x160)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x164)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x168)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x16C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x170)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x174)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x178)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x17C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x180)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x184)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x188)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x18C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x190)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x194)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x198)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x19C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_28_REG (CSR_QU_STFISCH_CSR_BASE + 0x1A0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_29_REG (CSR_QU_STFISCH_CSR_BASE + 0x1A4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_30_REG (CSR_QU_STFISCH_CSR_BASE + 0x1A8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_31_REG (CSR_QU_STFISCH_CSR_BASE + 0x1AC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_32_REG (CSR_QU_STFISCH_CSR_BASE + 0x1B0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_33_REG (CSR_QU_STFISCH_CSR_BASE + 0x1B4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_34_REG (CSR_QU_STFISCH_CSR_BASE + 0x1B8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_35_REG (CSR_QU_STFISCH_CSR_BASE + 0x1BC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_36_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_37_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_38_REG (CSR_QU_STFISCH_CSR_BASE + 0x1C8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_39_REG (CSR_QU_STFISCH_CSR_BASE + 0x1CC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_40_REG (CSR_QU_STFISCH_CSR_BASE + 0x1D0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_41_REG (CSR_QU_STFISCH_CSR_BASE + 0x1D4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_42_REG (CSR_QU_STFISCH_CSR_BASE + 0x1D8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_43_REG (CSR_QU_STFISCH_CSR_BASE + 0x1DC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_44_REG (CSR_QU_STFISCH_CSR_BASE + 0x1E0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_45_REG (CSR_QU_STFISCH_CSR_BASE + 0x1E4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_46_REG (CSR_QU_STFISCH_CSR_BASE + 0x1E8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_47_REG (CSR_QU_STFISCH_CSR_BASE + 0x1EC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_48_REG (CSR_QU_STFISCH_CSR_BASE + 0x1F0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_49_REG (CSR_QU_STFISCH_CSR_BASE + 0x1F4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_50_REG (CSR_QU_STFISCH_CSR_BASE + 0x1F8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_51_REG (CSR_QU_STFISCH_CSR_BASE + 0x1FC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_52_REG (CSR_QU_STFISCH_CSR_BASE + 0x200)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_53_REG (CSR_QU_STFISCH_CSR_BASE + 0x204)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_54_REG (CSR_QU_STFISCH_CSR_BASE + 0x208)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_55_REG (CSR_QU_STFISCH_CSR_BASE + 0x20C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_56_REG (CSR_QU_STFISCH_CSR_BASE + 0x210)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_57_REG (CSR_QU_STFISCH_CSR_BASE + 0x214)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_58_REG (CSR_QU_STFISCH_CSR_BASE + 0x218)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_59_REG (CSR_QU_STFISCH_CSR_BASE + 0x21C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_60_REG (CSR_QU_STFISCH_CSR_BASE + 0x220)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_61_REG (CSR_QU_STFISCH_CSR_BASE + 0x224)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_62_REG (CSR_QU_STFISCH_CSR_BASE + 0x228)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_63_REG (CSR_QU_STFISCH_CSR_BASE + 0x22C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_64_REG (CSR_QU_STFISCH_CSR_BASE + 0x230)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_65_REG (CSR_QU_STFISCH_CSR_BASE + 0x234)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_66_REG (CSR_QU_STFISCH_CSR_BASE + 0x238)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_67_REG (CSR_QU_STFISCH_CSR_BASE + 0x23C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_68_REG (CSR_QU_STFISCH_CSR_BASE + 0x240)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_69_REG (CSR_QU_STFISCH_CSR_BASE + 0x244)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_70_REG (CSR_QU_STFISCH_CSR_BASE + 0x248)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_71_REG (CSR_QU_STFISCH_CSR_BASE + 0x24C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_72_REG (CSR_QU_STFISCH_CSR_BASE + 0x250)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_73_REG (CSR_QU_STFISCH_CSR_BASE + 0x254)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_74_REG (CSR_QU_STFISCH_CSR_BASE + 0x258)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_75_REG (CSR_QU_STFISCH_CSR_BASE + 0x25C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_76_REG (CSR_QU_STFISCH_CSR_BASE + 0x260)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_77_REG (CSR_QU_STFISCH_CSR_BASE + 0x264)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_78_REG (CSR_QU_STFISCH_CSR_BASE + 0x268)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_79_REG (CSR_QU_STFISCH_CSR_BASE + 0x26C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_80_REG (CSR_QU_STFISCH_CSR_BASE + 0x270)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_81_REG (CSR_QU_STFISCH_CSR_BASE + 0x274)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_82_REG (CSR_QU_STFISCH_CSR_BASE + 0x278)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_83_REG (CSR_QU_STFISCH_CSR_BASE + 0x27C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_84_REG (CSR_QU_STFISCH_CSR_BASE + 0x280)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_85_REG (CSR_QU_STFISCH_CSR_BASE + 0x284)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_86_REG (CSR_QU_STFISCH_CSR_BASE + 0x288)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_87_REG (CSR_QU_STFISCH_CSR_BASE + 0x28C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_88_REG (CSR_QU_STFISCH_CSR_BASE + 0x290)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_89_REG (CSR_QU_STFISCH_CSR_BASE + 0x294)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_90_REG (CSR_QU_STFISCH_CSR_BASE + 0x298)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_91_REG (CSR_QU_STFISCH_CSR_BASE + 0x29C)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_92_REG (CSR_QU_STFISCH_CSR_BASE + 0x2A0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_93_REG (CSR_QU_STFISCH_CSR_BASE + 0x2A4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_94_REG (CSR_QU_STFISCH_CSR_BASE + 0x2A8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_95_REG (CSR_QU_STFISCH_CSR_BASE + 0x2AC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_96_REG (CSR_QU_STFISCH_CSR_BASE + 0x2B0)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_97_REG (CSR_QU_STFISCH_CSR_BASE + 0x2B4)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_98_REG (CSR_QU_STFISCH_CSR_BASE + 0x2B8)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_99_REG (CSR_QU_STFISCH_CSR_BASE + 0x2BC)       /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_100_REG (CSR_QU_STFISCH_CSR_BASE + 0x2C0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_101_REG (CSR_QU_STFISCH_CSR_BASE + 0x2C4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_102_REG (CSR_QU_STFISCH_CSR_BASE + 0x2C8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_103_REG (CSR_QU_STFISCH_CSR_BASE + 0x2CC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_104_REG (CSR_QU_STFISCH_CSR_BASE + 0x2D0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_105_REG (CSR_QU_STFISCH_CSR_BASE + 0x2D4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_106_REG (CSR_QU_STFISCH_CSR_BASE + 0x2D8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_107_REG (CSR_QU_STFISCH_CSR_BASE + 0x2DC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_108_REG (CSR_QU_STFISCH_CSR_BASE + 0x2E0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_109_REG (CSR_QU_STFISCH_CSR_BASE + 0x2E4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_110_REG (CSR_QU_STFISCH_CSR_BASE + 0x2E8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_111_REG (CSR_QU_STFISCH_CSR_BASE + 0x2EC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_112_REG (CSR_QU_STFISCH_CSR_BASE + 0x2F0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_113_REG (CSR_QU_STFISCH_CSR_BASE + 0x2F4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_114_REG (CSR_QU_STFISCH_CSR_BASE + 0x2F8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_115_REG (CSR_QU_STFISCH_CSR_BASE + 0x2FC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_116_REG (CSR_QU_STFISCH_CSR_BASE + 0x300)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_117_REG (CSR_QU_STFISCH_CSR_BASE + 0x304)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_118_REG (CSR_QU_STFISCH_CSR_BASE + 0x308)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_119_REG (CSR_QU_STFISCH_CSR_BASE + 0x30C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_120_REG (CSR_QU_STFISCH_CSR_BASE + 0x310)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_121_REG (CSR_QU_STFISCH_CSR_BASE + 0x314)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_122_REG (CSR_QU_STFISCH_CSR_BASE + 0x318)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_123_REG (CSR_QU_STFISCH_CSR_BASE + 0x31C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_124_REG (CSR_QU_STFISCH_CSR_BASE + 0x320)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_125_REG (CSR_QU_STFISCH_CSR_BASE + 0x324)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_126_REG (CSR_QU_STFISCH_CSR_BASE + 0x328)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_127_REG (CSR_QU_STFISCH_CSR_BASE + 0x32C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_128_REG (CSR_QU_STFISCH_CSR_BASE + 0x330)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_129_REG (CSR_QU_STFISCH_CSR_BASE + 0x334)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_130_REG (CSR_QU_STFISCH_CSR_BASE + 0x338)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_131_REG (CSR_QU_STFISCH_CSR_BASE + 0x33C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_132_REG (CSR_QU_STFISCH_CSR_BASE + 0x340)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_133_REG (CSR_QU_STFISCH_CSR_BASE + 0x344)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_134_REG (CSR_QU_STFISCH_CSR_BASE + 0x348)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_135_REG (CSR_QU_STFISCH_CSR_BASE + 0x34C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_136_REG (CSR_QU_STFISCH_CSR_BASE + 0x350)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_137_REG (CSR_QU_STFISCH_CSR_BASE + 0x354)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_138_REG (CSR_QU_STFISCH_CSR_BASE + 0x358)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_139_REG (CSR_QU_STFISCH_CSR_BASE + 0x35C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_140_REG (CSR_QU_STFISCH_CSR_BASE + 0x360)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_141_REG (CSR_QU_STFISCH_CSR_BASE + 0x364)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_142_REG (CSR_QU_STFISCH_CSR_BASE + 0x368)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_143_REG (CSR_QU_STFISCH_CSR_BASE + 0x36C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_144_REG (CSR_QU_STFISCH_CSR_BASE + 0x370)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_145_REG (CSR_QU_STFISCH_CSR_BASE + 0x374)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_146_REG (CSR_QU_STFISCH_CSR_BASE + 0x378)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_147_REG (CSR_QU_STFISCH_CSR_BASE + 0x37C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_148_REG (CSR_QU_STFISCH_CSR_BASE + 0x380)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_149_REG (CSR_QU_STFISCH_CSR_BASE + 0x384)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_150_REG (CSR_QU_STFISCH_CSR_BASE + 0x388)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_151_REG (CSR_QU_STFISCH_CSR_BASE + 0x38C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_152_REG (CSR_QU_STFISCH_CSR_BASE + 0x390)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_153_REG (CSR_QU_STFISCH_CSR_BASE + 0x394)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_154_REG (CSR_QU_STFISCH_CSR_BASE + 0x398)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_155_REG (CSR_QU_STFISCH_CSR_BASE + 0x39C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_156_REG (CSR_QU_STFISCH_CSR_BASE + 0x3A0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_157_REG (CSR_QU_STFISCH_CSR_BASE + 0x3A4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_158_REG (CSR_QU_STFISCH_CSR_BASE + 0x3A8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_159_REG (CSR_QU_STFISCH_CSR_BASE + 0x3AC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_160_REG (CSR_QU_STFISCH_CSR_BASE + 0x3B0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_161_REG (CSR_QU_STFISCH_CSR_BASE + 0x3B4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_162_REG (CSR_QU_STFISCH_CSR_BASE + 0x3B8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_163_REG (CSR_QU_STFISCH_CSR_BASE + 0x3BC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_164_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_165_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_166_REG (CSR_QU_STFISCH_CSR_BASE + 0x3C8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_167_REG (CSR_QU_STFISCH_CSR_BASE + 0x3CC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_168_REG (CSR_QU_STFISCH_CSR_BASE + 0x3D0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_169_REG (CSR_QU_STFISCH_CSR_BASE + 0x3D4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_170_REG (CSR_QU_STFISCH_CSR_BASE + 0x3D8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_171_REG (CSR_QU_STFISCH_CSR_BASE + 0x3DC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_172_REG (CSR_QU_STFISCH_CSR_BASE + 0x3E0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_173_REG (CSR_QU_STFISCH_CSR_BASE + 0x3E4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_174_REG (CSR_QU_STFISCH_CSR_BASE + 0x3E8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_175_REG (CSR_QU_STFISCH_CSR_BASE + 0x3EC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_176_REG (CSR_QU_STFISCH_CSR_BASE + 0x3F0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_177_REG (CSR_QU_STFISCH_CSR_BASE + 0x3F4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_178_REG (CSR_QU_STFISCH_CSR_BASE + 0x3F8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_179_REG (CSR_QU_STFISCH_CSR_BASE + 0x3FC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_180_REG (CSR_QU_STFISCH_CSR_BASE + 0x400)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_181_REG (CSR_QU_STFISCH_CSR_BASE + 0x404)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_182_REG (CSR_QU_STFISCH_CSR_BASE + 0x408)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_183_REG (CSR_QU_STFISCH_CSR_BASE + 0x40C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_184_REG (CSR_QU_STFISCH_CSR_BASE + 0x410)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_185_REG (CSR_QU_STFISCH_CSR_BASE + 0x414)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_186_REG (CSR_QU_STFISCH_CSR_BASE + 0x418)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_187_REG (CSR_QU_STFISCH_CSR_BASE + 0x41C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_188_REG (CSR_QU_STFISCH_CSR_BASE + 0x420)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_189_REG (CSR_QU_STFISCH_CSR_BASE + 0x424)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_190_REG (CSR_QU_STFISCH_CSR_BASE + 0x428)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_191_REG (CSR_QU_STFISCH_CSR_BASE + 0x42C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_192_REG (CSR_QU_STFISCH_CSR_BASE + 0x430)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_193_REG (CSR_QU_STFISCH_CSR_BASE + 0x434)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_194_REG (CSR_QU_STFISCH_CSR_BASE + 0x438)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_195_REG (CSR_QU_STFISCH_CSR_BASE + 0x43C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_196_REG (CSR_QU_STFISCH_CSR_BASE + 0x440)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_197_REG (CSR_QU_STFISCH_CSR_BASE + 0x444)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_198_REG (CSR_QU_STFISCH_CSR_BASE + 0x448)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_199_REG (CSR_QU_STFISCH_CSR_BASE + 0x44C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_200_REG (CSR_QU_STFISCH_CSR_BASE + 0x450)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_201_REG (CSR_QU_STFISCH_CSR_BASE + 0x454)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_202_REG (CSR_QU_STFISCH_CSR_BASE + 0x458)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_203_REG (CSR_QU_STFISCH_CSR_BASE + 0x45C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_204_REG (CSR_QU_STFISCH_CSR_BASE + 0x460)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_205_REG (CSR_QU_STFISCH_CSR_BASE + 0x464)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_206_REG (CSR_QU_STFISCH_CSR_BASE + 0x468)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_207_REG (CSR_QU_STFISCH_CSR_BASE + 0x46C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_208_REG (CSR_QU_STFISCH_CSR_BASE + 0x470)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_209_REG (CSR_QU_STFISCH_CSR_BASE + 0x474)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_210_REG (CSR_QU_STFISCH_CSR_BASE + 0x478)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_211_REG (CSR_QU_STFISCH_CSR_BASE + 0x47C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_212_REG (CSR_QU_STFISCH_CSR_BASE + 0x480)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_213_REG (CSR_QU_STFISCH_CSR_BASE + 0x484)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_214_REG (CSR_QU_STFISCH_CSR_BASE + 0x488)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_215_REG (CSR_QU_STFISCH_CSR_BASE + 0x48C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_216_REG (CSR_QU_STFISCH_CSR_BASE + 0x490)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_217_REG (CSR_QU_STFISCH_CSR_BASE + 0x494)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_218_REG (CSR_QU_STFISCH_CSR_BASE + 0x498)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_219_REG (CSR_QU_STFISCH_CSR_BASE + 0x49C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_220_REG (CSR_QU_STFISCH_CSR_BASE + 0x4A0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_221_REG (CSR_QU_STFISCH_CSR_BASE + 0x4A4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_222_REG (CSR_QU_STFISCH_CSR_BASE + 0x4A8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_223_REG (CSR_QU_STFISCH_CSR_BASE + 0x4AC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_224_REG (CSR_QU_STFISCH_CSR_BASE + 0x4B0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_225_REG (CSR_QU_STFISCH_CSR_BASE + 0x4B4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_226_REG (CSR_QU_STFISCH_CSR_BASE + 0x4B8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_227_REG (CSR_QU_STFISCH_CSR_BASE + 0x4BC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_228_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_229_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_230_REG (CSR_QU_STFISCH_CSR_BASE + 0x4C8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_231_REG (CSR_QU_STFISCH_CSR_BASE + 0x4CC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_232_REG (CSR_QU_STFISCH_CSR_BASE + 0x4D0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_233_REG (CSR_QU_STFISCH_CSR_BASE + 0x4D4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_234_REG (CSR_QU_STFISCH_CSR_BASE + 0x4D8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_235_REG (CSR_QU_STFISCH_CSR_BASE + 0x4DC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_236_REG (CSR_QU_STFISCH_CSR_BASE + 0x4E0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_237_REG (CSR_QU_STFISCH_CSR_BASE + 0x4E4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_238_REG (CSR_QU_STFISCH_CSR_BASE + 0x4E8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_239_REG (CSR_QU_STFISCH_CSR_BASE + 0x4EC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_240_REG (CSR_QU_STFISCH_CSR_BASE + 0x4F0)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_241_REG (CSR_QU_STFISCH_CSR_BASE + 0x4F4)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_242_REG (CSR_QU_STFISCH_CSR_BASE + 0x4F8)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_243_REG (CSR_QU_STFISCH_CSR_BASE + 0x4FC)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_244_REG (CSR_QU_STFISCH_CSR_BASE + 0x500)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_245_REG (CSR_QU_STFISCH_CSR_BASE + 0x504)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_246_REG (CSR_QU_STFISCH_CSR_BASE + 0x508)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_247_REG (CSR_QU_STFISCH_CSR_BASE + 0x50C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_248_REG (CSR_QU_STFISCH_CSR_BASE + 0x510)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_249_REG (CSR_QU_STFISCH_CSR_BASE + 0x514)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_250_REG (CSR_QU_STFISCH_CSR_BASE + 0x518)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_251_REG (CSR_QU_STFISCH_CSR_BASE + 0x51C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_252_REG (CSR_QU_STFISCH_CSR_BASE + 0x520)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_253_REG (CSR_QU_STFISCH_CSR_BASE + 0x524)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_254_REG (CSR_QU_STFISCH_CSR_BASE + 0x528)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_CHANNEL_CFG_255_REG (CSR_QU_STFISCH_CSR_BASE + 0x52C)      /* channel属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x530)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x534)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x538)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x53C)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x540)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x544)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x548)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x54C)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x550)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x554)            /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x558)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x55C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x560)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x564)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x568)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x56C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x570)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x574)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x578)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x57C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x580)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x584)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x588)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x58C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x590)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x594)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x598)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x59C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_28_REG (CSR_QU_STFISCH_CSR_BASE + 0x5A0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_29_REG (CSR_QU_STFISCH_CSR_BASE + 0x5A4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_30_REG (CSR_QU_STFISCH_CSR_BASE + 0x5A8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_31_REG (CSR_QU_STFISCH_CSR_BASE + 0x5AC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_32_REG (CSR_QU_STFISCH_CSR_BASE + 0x5B0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_33_REG (CSR_QU_STFISCH_CSR_BASE + 0x5B4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_34_REG (CSR_QU_STFISCH_CSR_BASE + 0x5B8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_35_REG (CSR_QU_STFISCH_CSR_BASE + 0x5BC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_36_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_37_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_38_REG (CSR_QU_STFISCH_CSR_BASE + 0x5C8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_39_REG (CSR_QU_STFISCH_CSR_BASE + 0x5CC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_40_REG (CSR_QU_STFISCH_CSR_BASE + 0x5D0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_41_REG (CSR_QU_STFISCH_CSR_BASE + 0x5D4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_42_REG (CSR_QU_STFISCH_CSR_BASE + 0x5D8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_43_REG (CSR_QU_STFISCH_CSR_BASE + 0x5DC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_44_REG (CSR_QU_STFISCH_CSR_BASE + 0x5E0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_45_REG (CSR_QU_STFISCH_CSR_BASE + 0x5E4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_46_REG (CSR_QU_STFISCH_CSR_BASE + 0x5E8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_47_REG (CSR_QU_STFISCH_CSR_BASE + 0x5EC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_48_REG (CSR_QU_STFISCH_CSR_BASE + 0x5F0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_49_REG (CSR_QU_STFISCH_CSR_BASE + 0x5F4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_50_REG (CSR_QU_STFISCH_CSR_BASE + 0x5F8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_51_REG (CSR_QU_STFISCH_CSR_BASE + 0x5FC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_52_REG (CSR_QU_STFISCH_CSR_BASE + 0x600)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_53_REG (CSR_QU_STFISCH_CSR_BASE + 0x604)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_54_REG (CSR_QU_STFISCH_CSR_BASE + 0x608)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_55_REG (CSR_QU_STFISCH_CSR_BASE + 0x60C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_56_REG (CSR_QU_STFISCH_CSR_BASE + 0x610)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_57_REG (CSR_QU_STFISCH_CSR_BASE + 0x614)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_58_REG (CSR_QU_STFISCH_CSR_BASE + 0x618)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_59_REG (CSR_QU_STFISCH_CSR_BASE + 0x61C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_60_REG (CSR_QU_STFISCH_CSR_BASE + 0x620)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_61_REG (CSR_QU_STFISCH_CSR_BASE + 0x624)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_62_REG (CSR_QU_STFISCH_CSR_BASE + 0x628)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_63_REG (CSR_QU_STFISCH_CSR_BASE + 0x62C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_64_REG (CSR_QU_STFISCH_CSR_BASE + 0x630)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_65_REG (CSR_QU_STFISCH_CSR_BASE + 0x634)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_66_REG (CSR_QU_STFISCH_CSR_BASE + 0x638)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_67_REG (CSR_QU_STFISCH_CSR_BASE + 0x63C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_68_REG (CSR_QU_STFISCH_CSR_BASE + 0x640)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_69_REG (CSR_QU_STFISCH_CSR_BASE + 0x644)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_70_REG (CSR_QU_STFISCH_CSR_BASE + 0x648)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_71_REG (CSR_QU_STFISCH_CSR_BASE + 0x64C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_72_REG (CSR_QU_STFISCH_CSR_BASE + 0x650)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_73_REG (CSR_QU_STFISCH_CSR_BASE + 0x654)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_74_REG (CSR_QU_STFISCH_CSR_BASE + 0x658)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_75_REG (CSR_QU_STFISCH_CSR_BASE + 0x65C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_76_REG (CSR_QU_STFISCH_CSR_BASE + 0x660)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_77_REG (CSR_QU_STFISCH_CSR_BASE + 0x664)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_78_REG (CSR_QU_STFISCH_CSR_BASE + 0x668)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_79_REG (CSR_QU_STFISCH_CSR_BASE + 0x66C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_80_REG (CSR_QU_STFISCH_CSR_BASE + 0x670)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_81_REG (CSR_QU_STFISCH_CSR_BASE + 0x674)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_82_REG (CSR_QU_STFISCH_CSR_BASE + 0x678)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_83_REG (CSR_QU_STFISCH_CSR_BASE + 0x67C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_84_REG (CSR_QU_STFISCH_CSR_BASE + 0x680)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_85_REG (CSR_QU_STFISCH_CSR_BASE + 0x684)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_86_REG (CSR_QU_STFISCH_CSR_BASE + 0x688)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_87_REG (CSR_QU_STFISCH_CSR_BASE + 0x68C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_88_REG (CSR_QU_STFISCH_CSR_BASE + 0x690)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_89_REG (CSR_QU_STFISCH_CSR_BASE + 0x694)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_90_REG (CSR_QU_STFISCH_CSR_BASE + 0x698)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_91_REG (CSR_QU_STFISCH_CSR_BASE + 0x69C)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_92_REG (CSR_QU_STFISCH_CSR_BASE + 0x6A0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_93_REG (CSR_QU_STFISCH_CSR_BASE + 0x6A4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_94_REG (CSR_QU_STFISCH_CSR_BASE + 0x6A8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_95_REG (CSR_QU_STFISCH_CSR_BASE + 0x6AC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_96_REG (CSR_QU_STFISCH_CSR_BASE + 0x6B0)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_97_REG (CSR_QU_STFISCH_CSR_BASE + 0x6B4)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_98_REG (CSR_QU_STFISCH_CSR_BASE + 0x6B8)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_99_REG (CSR_QU_STFISCH_CSR_BASE + 0x6BC)           /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_100_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_101_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_102_REG (CSR_QU_STFISCH_CSR_BASE + 0x6C8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_103_REG (CSR_QU_STFISCH_CSR_BASE + 0x6CC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_104_REG (CSR_QU_STFISCH_CSR_BASE + 0x6D0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_105_REG (CSR_QU_STFISCH_CSR_BASE + 0x6D4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_106_REG (CSR_QU_STFISCH_CSR_BASE + 0x6D8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_107_REG (CSR_QU_STFISCH_CSR_BASE + 0x6DC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_108_REG (CSR_QU_STFISCH_CSR_BASE + 0x6E0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_109_REG (CSR_QU_STFISCH_CSR_BASE + 0x6E4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_110_REG (CSR_QU_STFISCH_CSR_BASE + 0x6E8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_111_REG (CSR_QU_STFISCH_CSR_BASE + 0x6EC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_112_REG (CSR_QU_STFISCH_CSR_BASE + 0x6F0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_113_REG (CSR_QU_STFISCH_CSR_BASE + 0x6F4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_114_REG (CSR_QU_STFISCH_CSR_BASE + 0x6F8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_115_REG (CSR_QU_STFISCH_CSR_BASE + 0x6FC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_116_REG (CSR_QU_STFISCH_CSR_BASE + 0x700)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_117_REG (CSR_QU_STFISCH_CSR_BASE + 0x704)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_118_REG (CSR_QU_STFISCH_CSR_BASE + 0x708)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_119_REG (CSR_QU_STFISCH_CSR_BASE + 0x70C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_120_REG (CSR_QU_STFISCH_CSR_BASE + 0x710)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_121_REG (CSR_QU_STFISCH_CSR_BASE + 0x714)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_122_REG (CSR_QU_STFISCH_CSR_BASE + 0x718)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_123_REG (CSR_QU_STFISCH_CSR_BASE + 0x71C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_124_REG (CSR_QU_STFISCH_CSR_BASE + 0x720)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_125_REG (CSR_QU_STFISCH_CSR_BASE + 0x724)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_126_REG (CSR_QU_STFISCH_CSR_BASE + 0x728)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_127_REG (CSR_QU_STFISCH_CSR_BASE + 0x72C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_128_REG (CSR_QU_STFISCH_CSR_BASE + 0x730)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_129_REG (CSR_QU_STFISCH_CSR_BASE + 0x734)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_130_REG (CSR_QU_STFISCH_CSR_BASE + 0x738)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_131_REG (CSR_QU_STFISCH_CSR_BASE + 0x73C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_132_REG (CSR_QU_STFISCH_CSR_BASE + 0x740)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_133_REG (CSR_QU_STFISCH_CSR_BASE + 0x744)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_134_REG (CSR_QU_STFISCH_CSR_BASE + 0x748)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_135_REG (CSR_QU_STFISCH_CSR_BASE + 0x74C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_136_REG (CSR_QU_STFISCH_CSR_BASE + 0x750)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_137_REG (CSR_QU_STFISCH_CSR_BASE + 0x754)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_138_REG (CSR_QU_STFISCH_CSR_BASE + 0x758)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_139_REG (CSR_QU_STFISCH_CSR_BASE + 0x75C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_140_REG (CSR_QU_STFISCH_CSR_BASE + 0x760)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_141_REG (CSR_QU_STFISCH_CSR_BASE + 0x764)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_142_REG (CSR_QU_STFISCH_CSR_BASE + 0x768)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_143_REG (CSR_QU_STFISCH_CSR_BASE + 0x76C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_144_REG (CSR_QU_STFISCH_CSR_BASE + 0x770)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_145_REG (CSR_QU_STFISCH_CSR_BASE + 0x774)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_146_REG (CSR_QU_STFISCH_CSR_BASE + 0x778)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_147_REG (CSR_QU_STFISCH_CSR_BASE + 0x77C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_148_REG (CSR_QU_STFISCH_CSR_BASE + 0x780)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_149_REG (CSR_QU_STFISCH_CSR_BASE + 0x784)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_150_REG (CSR_QU_STFISCH_CSR_BASE + 0x788)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_151_REG (CSR_QU_STFISCH_CSR_BASE + 0x78C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_152_REG (CSR_QU_STFISCH_CSR_BASE + 0x790)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_153_REG (CSR_QU_STFISCH_CSR_BASE + 0x794)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_154_REG (CSR_QU_STFISCH_CSR_BASE + 0x798)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_155_REG (CSR_QU_STFISCH_CSR_BASE + 0x79C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_156_REG (CSR_QU_STFISCH_CSR_BASE + 0x7A0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_157_REG (CSR_QU_STFISCH_CSR_BASE + 0x7A4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_158_REG (CSR_QU_STFISCH_CSR_BASE + 0x7A8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_159_REG (CSR_QU_STFISCH_CSR_BASE + 0x7AC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_160_REG (CSR_QU_STFISCH_CSR_BASE + 0x7B0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_161_REG (CSR_QU_STFISCH_CSR_BASE + 0x7B4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_162_REG (CSR_QU_STFISCH_CSR_BASE + 0x7B8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_163_REG (CSR_QU_STFISCH_CSR_BASE + 0x7BC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_164_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_165_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_166_REG (CSR_QU_STFISCH_CSR_BASE + 0x7C8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_167_REG (CSR_QU_STFISCH_CSR_BASE + 0x7CC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_168_REG (CSR_QU_STFISCH_CSR_BASE + 0x7D0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_169_REG (CSR_QU_STFISCH_CSR_BASE + 0x7D4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_170_REG (CSR_QU_STFISCH_CSR_BASE + 0x7D8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_171_REG (CSR_QU_STFISCH_CSR_BASE + 0x7DC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_172_REG (CSR_QU_STFISCH_CSR_BASE + 0x7E0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_173_REG (CSR_QU_STFISCH_CSR_BASE + 0x7E4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_174_REG (CSR_QU_STFISCH_CSR_BASE + 0x7E8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_175_REG (CSR_QU_STFISCH_CSR_BASE + 0x7EC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_176_REG (CSR_QU_STFISCH_CSR_BASE + 0x7F0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_177_REG (CSR_QU_STFISCH_CSR_BASE + 0x7F4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_178_REG (CSR_QU_STFISCH_CSR_BASE + 0x7F8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_179_REG (CSR_QU_STFISCH_CSR_BASE + 0x7FC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_180_REG (CSR_QU_STFISCH_CSR_BASE + 0x800)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_181_REG (CSR_QU_STFISCH_CSR_BASE + 0x804)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_182_REG (CSR_QU_STFISCH_CSR_BASE + 0x808)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_183_REG (CSR_QU_STFISCH_CSR_BASE + 0x80C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_184_REG (CSR_QU_STFISCH_CSR_BASE + 0x810)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_185_REG (CSR_QU_STFISCH_CSR_BASE + 0x814)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_186_REG (CSR_QU_STFISCH_CSR_BASE + 0x818)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_187_REG (CSR_QU_STFISCH_CSR_BASE + 0x81C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_188_REG (CSR_QU_STFISCH_CSR_BASE + 0x820)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_189_REG (CSR_QU_STFISCH_CSR_BASE + 0x824)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_190_REG (CSR_QU_STFISCH_CSR_BASE + 0x828)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_191_REG (CSR_QU_STFISCH_CSR_BASE + 0x82C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_192_REG (CSR_QU_STFISCH_CSR_BASE + 0x830)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_193_REG (CSR_QU_STFISCH_CSR_BASE + 0x834)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_194_REG (CSR_QU_STFISCH_CSR_BASE + 0x838)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_195_REG (CSR_QU_STFISCH_CSR_BASE + 0x83C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_196_REG (CSR_QU_STFISCH_CSR_BASE + 0x840)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_197_REG (CSR_QU_STFISCH_CSR_BASE + 0x844)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_198_REG (CSR_QU_STFISCH_CSR_BASE + 0x848)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_199_REG (CSR_QU_STFISCH_CSR_BASE + 0x84C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_200_REG (CSR_QU_STFISCH_CSR_BASE + 0x850)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_201_REG (CSR_QU_STFISCH_CSR_BASE + 0x854)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_202_REG (CSR_QU_STFISCH_CSR_BASE + 0x858)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_203_REG (CSR_QU_STFISCH_CSR_BASE + 0x85C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_204_REG (CSR_QU_STFISCH_CSR_BASE + 0x860)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_205_REG (CSR_QU_STFISCH_CSR_BASE + 0x864)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_206_REG (CSR_QU_STFISCH_CSR_BASE + 0x868)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_207_REG (CSR_QU_STFISCH_CSR_BASE + 0x86C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_208_REG (CSR_QU_STFISCH_CSR_BASE + 0x870)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_209_REG (CSR_QU_STFISCH_CSR_BASE + 0x874)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_210_REG (CSR_QU_STFISCH_CSR_BASE + 0x878)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_211_REG (CSR_QU_STFISCH_CSR_BASE + 0x87C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_212_REG (CSR_QU_STFISCH_CSR_BASE + 0x880)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_213_REG (CSR_QU_STFISCH_CSR_BASE + 0x884)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_214_REG (CSR_QU_STFISCH_CSR_BASE + 0x888)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_215_REG (CSR_QU_STFISCH_CSR_BASE + 0x88C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_216_REG (CSR_QU_STFISCH_CSR_BASE + 0x890)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_217_REG (CSR_QU_STFISCH_CSR_BASE + 0x894)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_218_REG (CSR_QU_STFISCH_CSR_BASE + 0x898)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_219_REG (CSR_QU_STFISCH_CSR_BASE + 0x89C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_220_REG (CSR_QU_STFISCH_CSR_BASE + 0x8A0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_221_REG (CSR_QU_STFISCH_CSR_BASE + 0x8A4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_222_REG (CSR_QU_STFISCH_CSR_BASE + 0x8A8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_223_REG (CSR_QU_STFISCH_CSR_BASE + 0x8AC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_224_REG (CSR_QU_STFISCH_CSR_BASE + 0x8B0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_225_REG (CSR_QU_STFISCH_CSR_BASE + 0x8B4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_226_REG (CSR_QU_STFISCH_CSR_BASE + 0x8B8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_227_REG (CSR_QU_STFISCH_CSR_BASE + 0x8BC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_228_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_229_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_230_REG (CSR_QU_STFISCH_CSR_BASE + 0x8C8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_231_REG (CSR_QU_STFISCH_CSR_BASE + 0x8CC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_232_REG (CSR_QU_STFISCH_CSR_BASE + 0x8D0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_233_REG (CSR_QU_STFISCH_CSR_BASE + 0x8D4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_234_REG (CSR_QU_STFISCH_CSR_BASE + 0x8D8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_235_REG (CSR_QU_STFISCH_CSR_BASE + 0x8DC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_236_REG (CSR_QU_STFISCH_CSR_BASE + 0x8E0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_237_REG (CSR_QU_STFISCH_CSR_BASE + 0x8E4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_238_REG (CSR_QU_STFISCH_CSR_BASE + 0x8E8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_239_REG (CSR_QU_STFISCH_CSR_BASE + 0x8EC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_240_REG (CSR_QU_STFISCH_CSR_BASE + 0x8F0)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_241_REG (CSR_QU_STFISCH_CSR_BASE + 0x8F4)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_242_REG (CSR_QU_STFISCH_CSR_BASE + 0x8F8)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_243_REG (CSR_QU_STFISCH_CSR_BASE + 0x8FC)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_244_REG (CSR_QU_STFISCH_CSR_BASE + 0x900)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_245_REG (CSR_QU_STFISCH_CSR_BASE + 0x904)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_246_REG (CSR_QU_STFISCH_CSR_BASE + 0x908)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_247_REG (CSR_QU_STFISCH_CSR_BASE + 0x90C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_248_REG (CSR_QU_STFISCH_CSR_BASE + 0x910)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_249_REG (CSR_QU_STFISCH_CSR_BASE + 0x914)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_250_REG (CSR_QU_STFISCH_CSR_BASE + 0x918)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_251_REG (CSR_QU_STFISCH_CSR_BASE + 0x91C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_252_REG (CSR_QU_STFISCH_CSR_BASE + 0x920)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_253_REG (CSR_QU_STFISCH_CSR_BASE + 0x924)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_254_REG (CSR_QU_STFISCH_CSR_BASE + 0x928)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_4IQ_CFG_255_REG (CSR_QU_STFISCH_CSR_BASE + 0x92C)          /* IQ属性配置 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_0_REG (CSR_QU_STFISCH_CSR_BASE + 0x950)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_1_REG (CSR_QU_STFISCH_CSR_BASE + 0x954)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_2_REG (CSR_QU_STFISCH_CSR_BASE + 0x958)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_3_REG (CSR_QU_STFISCH_CSR_BASE + 0x95C)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_4_REG (CSR_QU_STFISCH_CSR_BASE + 0x960)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_5_REG (CSR_QU_STFISCH_CSR_BASE + 0x964)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_6_REG (CSR_QU_STFISCH_CSR_BASE + 0x968)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_7_REG (CSR_QU_STFISCH_CSR_BASE + 0x96C)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_8_REG (CSR_QU_STFISCH_CSR_BASE + 0x970)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_9_REG (CSR_QU_STFISCH_CSR_BASE + 0x974)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_10_REG (CSR_QU_STFISCH_CSR_BASE + 0x978)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_11_REG (CSR_QU_STFISCH_CSR_BASE + 0x97C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_12_REG (CSR_QU_STFISCH_CSR_BASE + 0x980)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_13_REG (CSR_QU_STFISCH_CSR_BASE + 0x984)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_14_REG (CSR_QU_STFISCH_CSR_BASE + 0x988)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_15_REG (CSR_QU_STFISCH_CSR_BASE + 0x98C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_16_REG (CSR_QU_STFISCH_CSR_BASE + 0x990)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_17_REG (CSR_QU_STFISCH_CSR_BASE + 0x994)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_18_REG (CSR_QU_STFISCH_CSR_BASE + 0x998)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_19_REG (CSR_QU_STFISCH_CSR_BASE + 0x99C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_20_REG (CSR_QU_STFISCH_CSR_BASE + 0x9A0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_21_REG (CSR_QU_STFISCH_CSR_BASE + 0x9A4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_22_REG (CSR_QU_STFISCH_CSR_BASE + 0x9A8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_23_REG (CSR_QU_STFISCH_CSR_BASE + 0x9AC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_24_REG (CSR_QU_STFISCH_CSR_BASE + 0x9B0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_25_REG (CSR_QU_STFISCH_CSR_BASE + 0x9B4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_26_REG (CSR_QU_STFISCH_CSR_BASE + 0x9B8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_27_REG (CSR_QU_STFISCH_CSR_BASE + 0x9BC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_28_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_29_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_30_REG (CSR_QU_STFISCH_CSR_BASE + 0x9C8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_31_REG (CSR_QU_STFISCH_CSR_BASE + 0x9CC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_32_REG (CSR_QU_STFISCH_CSR_BASE + 0x9D0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_33_REG (CSR_QU_STFISCH_CSR_BASE + 0x9D4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_34_REG (CSR_QU_STFISCH_CSR_BASE + 0x9D8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_35_REG (CSR_QU_STFISCH_CSR_BASE + 0x9DC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_36_REG (CSR_QU_STFISCH_CSR_BASE + 0x9E0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_37_REG (CSR_QU_STFISCH_CSR_BASE + 0x9E4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_38_REG (CSR_QU_STFISCH_CSR_BASE + 0x9E8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_39_REG (CSR_QU_STFISCH_CSR_BASE + 0x9EC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_40_REG (CSR_QU_STFISCH_CSR_BASE + 0x9F0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_41_REG (CSR_QU_STFISCH_CSR_BASE + 0x9F4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_42_REG (CSR_QU_STFISCH_CSR_BASE + 0x9F8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_43_REG (CSR_QU_STFISCH_CSR_BASE + 0x9FC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xA00)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xA04)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xA08)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xA0C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xA10)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xA14)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xA18)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xA1C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_52_REG (CSR_QU_STFISCH_CSR_BASE + 0xA20)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_53_REG (CSR_QU_STFISCH_CSR_BASE + 0xA24)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_54_REG (CSR_QU_STFISCH_CSR_BASE + 0xA28)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_55_REG (CSR_QU_STFISCH_CSR_BASE + 0xA2C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_56_REG (CSR_QU_STFISCH_CSR_BASE + 0xA30)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_57_REG (CSR_QU_STFISCH_CSR_BASE + 0xA34)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_58_REG (CSR_QU_STFISCH_CSR_BASE + 0xA38)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_59_REG (CSR_QU_STFISCH_CSR_BASE + 0xA3C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_60_REG (CSR_QU_STFISCH_CSR_BASE + 0xA40)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_61_REG (CSR_QU_STFISCH_CSR_BASE + 0xA44)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_62_REG (CSR_QU_STFISCH_CSR_BASE + 0xA48)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA1_63_REG (CSR_QU_STFISCH_CSR_BASE + 0xA4C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xA50)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xA54)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xA58)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xA5C)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_4_REG (CSR_QU_STFISCH_CSR_BASE + 0xA60)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_5_REG (CSR_QU_STFISCH_CSR_BASE + 0xA64)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_6_REG (CSR_QU_STFISCH_CSR_BASE + 0xA68)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_7_REG (CSR_QU_STFISCH_CSR_BASE + 0xA6C)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_8_REG (CSR_QU_STFISCH_CSR_BASE + 0xA70)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_9_REG (CSR_QU_STFISCH_CSR_BASE + 0xA74)           /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_10_REG (CSR_QU_STFISCH_CSR_BASE + 0xA78)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_11_REG (CSR_QU_STFISCH_CSR_BASE + 0xA7C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_12_REG (CSR_QU_STFISCH_CSR_BASE + 0xA80)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_13_REG (CSR_QU_STFISCH_CSR_BASE + 0xA84)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_14_REG (CSR_QU_STFISCH_CSR_BASE + 0xA88)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_15_REG (CSR_QU_STFISCH_CSR_BASE + 0xA8C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_16_REG (CSR_QU_STFISCH_CSR_BASE + 0xA90)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_17_REG (CSR_QU_STFISCH_CSR_BASE + 0xA94)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_18_REG (CSR_QU_STFISCH_CSR_BASE + 0xA98)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_19_REG (CSR_QU_STFISCH_CSR_BASE + 0xA9C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_20_REG (CSR_QU_STFISCH_CSR_BASE + 0xAA0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_21_REG (CSR_QU_STFISCH_CSR_BASE + 0xAA4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_22_REG (CSR_QU_STFISCH_CSR_BASE + 0xAA8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_23_REG (CSR_QU_STFISCH_CSR_BASE + 0xAAC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_24_REG (CSR_QU_STFISCH_CSR_BASE + 0xAB0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_25_REG (CSR_QU_STFISCH_CSR_BASE + 0xAB4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_26_REG (CSR_QU_STFISCH_CSR_BASE + 0xAB8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_27_REG (CSR_QU_STFISCH_CSR_BASE + 0xABC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_28_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_29_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_30_REG (CSR_QU_STFISCH_CSR_BASE + 0xAC8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_31_REG (CSR_QU_STFISCH_CSR_BASE + 0xACC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_32_REG (CSR_QU_STFISCH_CSR_BASE + 0xAD0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_33_REG (CSR_QU_STFISCH_CSR_BASE + 0xAD4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_34_REG (CSR_QU_STFISCH_CSR_BASE + 0xAD8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_35_REG (CSR_QU_STFISCH_CSR_BASE + 0xADC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_36_REG (CSR_QU_STFISCH_CSR_BASE + 0xAE0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_37_REG (CSR_QU_STFISCH_CSR_BASE + 0xAE4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_38_REG (CSR_QU_STFISCH_CSR_BASE + 0xAE8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_39_REG (CSR_QU_STFISCH_CSR_BASE + 0xAEC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_40_REG (CSR_QU_STFISCH_CSR_BASE + 0xAF0)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_41_REG (CSR_QU_STFISCH_CSR_BASE + 0xAF4)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_42_REG (CSR_QU_STFISCH_CSR_BASE + 0xAF8)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_43_REG (CSR_QU_STFISCH_CSR_BASE + 0xAFC)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xB00)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xB04)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xB08)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xB0C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xB10)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xB14)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xB18)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xB1C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_52_REG (CSR_QU_STFISCH_CSR_BASE + 0xB20)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_53_REG (CSR_QU_STFISCH_CSR_BASE + 0xB24)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_54_REG (CSR_QU_STFISCH_CSR_BASE + 0xB28)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_55_REG (CSR_QU_STFISCH_CSR_BASE + 0xB2C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_56_REG (CSR_QU_STFISCH_CSR_BASE + 0xB30)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_57_REG (CSR_QU_STFISCH_CSR_BASE + 0xB34)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_58_REG (CSR_QU_STFISCH_CSR_BASE + 0xB38)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_59_REG (CSR_QU_STFISCH_CSR_BASE + 0xB3C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_60_REG (CSR_QU_STFISCH_CSR_BASE + 0xB40)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_61_REG (CSR_QU_STFISCH_CSR_BASE + 0xB44)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_62_REG (CSR_QU_STFISCH_CSR_BASE + 0xB48)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_2TH_STA2_63_REG (CSR_QU_STFISCH_CSR_BASE + 0xB4C)          /* 线程状态寄存器 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xB50)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xB54)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xB58)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xB5C)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_4_REG (CSR_QU_STFISCH_CSR_BASE + 0xB60)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_5_REG (CSR_QU_STFISCH_CSR_BASE + 0xB64)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_6_REG (CSR_QU_STFISCH_CSR_BASE + 0xB68)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_7_REG (CSR_QU_STFISCH_CSR_BASE + 0xB6C)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_8_REG (CSR_QU_STFISCH_CSR_BASE + 0xB70)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_9_REG (CSR_QU_STFISCH_CSR_BASE + 0xB74)          /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_10_REG (CSR_QU_STFISCH_CSR_BASE + 0xB78)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_11_REG (CSR_QU_STFISCH_CSR_BASE + 0xB7C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_12_REG (CSR_QU_STFISCH_CSR_BASE + 0xB80)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_13_REG (CSR_QU_STFISCH_CSR_BASE + 0xB84)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_14_REG (CSR_QU_STFISCH_CSR_BASE + 0xB88)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_15_REG (CSR_QU_STFISCH_CSR_BASE + 0xB8C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_16_REG (CSR_QU_STFISCH_CSR_BASE + 0xB90)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_17_REG (CSR_QU_STFISCH_CSR_BASE + 0xB94)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_18_REG (CSR_QU_STFISCH_CSR_BASE + 0xB98)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_19_REG (CSR_QU_STFISCH_CSR_BASE + 0xB9C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_20_REG (CSR_QU_STFISCH_CSR_BASE + 0xBA0)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_21_REG (CSR_QU_STFISCH_CSR_BASE + 0xBA4)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_22_REG (CSR_QU_STFISCH_CSR_BASE + 0xBA8)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_23_REG (CSR_QU_STFISCH_CSR_BASE + 0xBAC)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_24_REG (CSR_QU_STFISCH_CSR_BASE + 0xBB0)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_25_REG (CSR_QU_STFISCH_CSR_BASE + 0xBB4)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_26_REG (CSR_QU_STFISCH_CSR_BASE + 0xBB8)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_27_REG (CSR_QU_STFISCH_CSR_BASE + 0xBBC)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_28_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC0)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_29_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC4)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_30_REG (CSR_QU_STFISCH_CSR_BASE + 0xBC8)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_31_REG (CSR_QU_STFISCH_CSR_BASE + 0xBCC)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_32_REG (CSR_QU_STFISCH_CSR_BASE + 0xBD0)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_33_REG (CSR_QU_STFISCH_CSR_BASE + 0xBD4)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_34_REG (CSR_QU_STFISCH_CSR_BASE + 0xBD8)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_35_REG (CSR_QU_STFISCH_CSR_BASE + 0xBDC)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_36_REG (CSR_QU_STFISCH_CSR_BASE + 0xBE0)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_37_REG (CSR_QU_STFISCH_CSR_BASE + 0xBE4)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_38_REG (CSR_QU_STFISCH_CSR_BASE + 0xBE8)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_39_REG (CSR_QU_STFISCH_CSR_BASE + 0xBEC)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_40_REG (CSR_QU_STFISCH_CSR_BASE + 0xBF0)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_41_REG (CSR_QU_STFISCH_CSR_BASE + 0xBF4)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_42_REG (CSR_QU_STFISCH_CSR_BASE + 0xBF8)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_43_REG (CSR_QU_STFISCH_CSR_BASE + 0xBFC)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_44_REG (CSR_QU_STFISCH_CSR_BASE + 0xC00)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_45_REG (CSR_QU_STFISCH_CSR_BASE + 0xC04)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_46_REG (CSR_QU_STFISCH_CSR_BASE + 0xC08)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_47_REG (CSR_QU_STFISCH_CSR_BASE + 0xC0C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_48_REG (CSR_QU_STFISCH_CSR_BASE + 0xC10)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_49_REG (CSR_QU_STFISCH_CSR_BASE + 0xC14)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_50_REG (CSR_QU_STFISCH_CSR_BASE + 0xC18)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_51_REG (CSR_QU_STFISCH_CSR_BASE + 0xC1C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_52_REG (CSR_QU_STFISCH_CSR_BASE + 0xC20)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_53_REG (CSR_QU_STFISCH_CSR_BASE + 0xC24)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_54_REG (CSR_QU_STFISCH_CSR_BASE + 0xC28)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_55_REG (CSR_QU_STFISCH_CSR_BASE + 0xC2C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_56_REG (CSR_QU_STFISCH_CSR_BASE + 0xC30)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_57_REG (CSR_QU_STFISCH_CSR_BASE + 0xC34)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_58_REG (CSR_QU_STFISCH_CSR_BASE + 0xC38)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_59_REG (CSR_QU_STFISCH_CSR_BASE + 0xC3C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_60_REG (CSR_QU_STFISCH_CSR_BASE + 0xC40)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_61_REG (CSR_QU_STFISCH_CSR_BASE + 0xC44)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_62_REG (CSR_QU_STFISCH_CSR_BASE + 0xC48)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_CORE0_STA_63_REG (CSR_QU_STFISCH_CSR_BASE + 0xC4C)         /* core线程watch_dog状态 */
#define CSR_QU_STFISCH_CSR_ISCH_RLS_C_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC54)         /* 释放线程状态错误计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TIME_OUT_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC58)      /* 超时错误计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TH_RLS_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC5C)        /* 释放线程总数计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TH_ALC_CNT_REG (CSR_QU_STFISCH_CSR_BASE + 0xC60)        /* 分配线程总数计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xC64)  /* 分配线程总数计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xC68)  /* 分配线程总数计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xC6C)  /* 分配线程总数计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_TL_IDLE_TH_CNT_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xC70)  /* 分配线程总数计数器。 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_EN_REG (CSR_QU_STFISCH_CSR_BASE + 0xC74) /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_0_REG (CSR_QU_STFISCH_CSR_BASE + 0xC78)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_1_REG (CSR_QU_STFISCH_CSR_BASE + 0xC7C)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_2_REG (CSR_QU_STFISCH_CSR_BASE + 0xC80)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_3_REG (CSR_QU_STFISCH_CSR_BASE + 0xC84)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_4_REG (CSR_QU_STFISCH_CSR_BASE + 0xC88)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_5_REG (CSR_QU_STFISCH_CSR_BASE + 0xC8C)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_6_REG (CSR_QU_STFISCH_CSR_BASE + 0xC90)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_7_REG (CSR_QU_STFISCH_CSR_BASE + 0xC94)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_8_REG (CSR_QU_STFISCH_CSR_BASE + 0xC98)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_9_REG (CSR_QU_STFISCH_CSR_BASE + 0xC9C)  /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_10_REG (CSR_QU_STFISCH_CSR_BASE + 0xCA0) /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_11_REG (CSR_QU_STFISCH_CSR_BASE + 0xCA4) /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_12_REG (CSR_QU_STFISCH_CSR_BASE + 0xCA8) /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_13_REG (CSR_QU_STFISCH_CSR_BASE + 0xCAC) /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_14_REG (CSR_QU_STFISCH_CSR_BASE + 0xCB0) /* ScoreBoard 配置 */
#define CSR_QU_STFISCH_CSR_ISCH_SCOREBOARD_CFG_15_REG (CSR_QU_STFISCH_CSR_BASE + 0xCB4) /* ScoreBoard 配置 */

#endif // STFISCH_REG_OFFSET_H
